Burst error detection and correction system

ABSTRACT

A data communication system has a source of data. The data is divided into data segments. When a burst error is indicated, the location of the burst error is determined and the burst error is corrected.

United States Patent Blair et al.

1111 3,725,859 1451 Apr. 3, '1973 [54] 3,478,313 11/1969 Srinivasan ..340/l46.l AL CORRECTION SYSTEM 3,123,803 3/1964 De Lisle et al. ..340/l46.l AL 3,222,643 l2/l965 Klinkhamer ..340/l46.l AL [751' lnvvemors- Charles malrnauas Fnmk 3,418,630 12/1968 Van Duuren... ..340/146,1 AL

Hmlston v 3,542,756 11 1970 Gallager ..340/l46.1 AL 73 Assignee; Texas Instruments Incorporated, 3,544,963 12/1970 Tong ..340/146.l AL

Dallas, Tex.

Primary Examiner-Charles E. Atkinson 22 F1led: une 14 1971 l 1 J Attorney-James O. Dlxon et al, [21] Appl. No.: 152,941

57 AB TRACT [52] U.S. Cl. ..340/l46.l AL 1 s [51] Int.Cl ..G06f 11/12 A data communication 5 ystem has a source of data. [58] Field of Search ..340/l46.1 AL, 172.5 The data is divided into data segmema when a burst error is indicated, the location of the burst error is [56] Refemnces Clted determined and the burst error is corrected. UNITED STATES PATENTS v v v I 3,487,362 12/1969 Frey, Jr ..340/146.1 AL 4 Claims, 44 Drawing Figures 66' 67 RM'D SHIFTSIRZEZIILTER a I 5.9 PARITY WORD SERIAL T GENERATOR v OUTPUT wmo CONTROL 66 63 57 sERl L cHEcK WORD ERROR RDD PuT GENERATOR CORRECTION CONTROL 1 1:22:? 53

READ CHECK WORD 55 REGISTER 89TFA-WDI 5H".-|-

9lTFA- RMI COUNTER 93TFA-WMD p l COMPARE 95TFA-RDO TRACK '54 22 STAT l CONTROL BESA STAT 2 REGISTER 7.9 55 v 3/ CMDB! i TSTAL' 83 CMDB z T 5111;:

saE I CORRECTION g 64 BURST TDE ERROR DETECT E75 99 BDE l 56 PEG BURST ERROR DETECTION AND PATENTEDAPR3 1973 2 ,859

SHEEI U1UF25 512 a T RMID a I Z wM D SHIFT REGISTER 59 PARITY woRD J SERIAL GENERATOR OUTPUT CONTROL 66 SERIAL CHECK WORD a ERROR RIM mpu-r GENERATOR CORRECTION CONTROL A k l 9 READ PARITY WORD REGISTER 52 READ CHECK WORD -55 REGISTER 89TFA-WDI SHIFT 62 91TFA- RMI COUNTER 93TFA-WMD L COMPARE ,54 Se AND QSTFA- BESA STAT CONTROL BESA STAT 2 REGlSTER' 7.9 a5

) T STAT 8/ CMDEI T STAT 83 (WIDE 2 L 9 SEE coRREcTloN' 7/ BURST TDE l ,1 ERROR I DETECT Fly 1 r BDE 1 56 PEG I lo/ PM A. M

EXCLUSIVE OR NOR AND

AND/OR INVERTER Fig, 2

PATENTEDAPRS 191a SHEET UUUF 26 Eommu .rmmnmv mPm TUNE DEO XUUIU UZFZZDD PATENTEUAPR3 I975 SHEET 078F 26 PATENTEUAPR3 I973 SHEET 08 0F 26 won-m PATENTEUAPR3 I973 ,725, 59

SHEET 110F26 WRITE DATA INPUT (528 CLOCKS) FEEDBACK ENABLE CHECK 0 1 2 WORD ou'r ENCODER (l0 CLOCKS) Fig /30 READ MESSAGE o 1 2 3 4 5 s 7 s 9 INPUT (s38 CL K DECODER /35 Fig /3b /4/ l o 1 2 3 4 s s 7 a 9 ERROR SYNDROME MULTIPLIER ENCODE TRACK DATA WORD FEEDBACK ENABLE DECODE o 1 z 3 4 s 6 7 s 9 TRACK I CHECK CODEWORD L35 WORD COMBINED ENCODER/DECODER/MULTIPLIER ou'r AM n PATENTEDAPR3 191s SHEET 1U UF 26 DQGEOMD PATENTEDAPR3 um SHEET 150F26 mOUm mmZm

WFE mm 5Q PATENTEDAPR3 I975 25, 59

ATBCR ST- EIIB 0 HIIEHBBH I O O SHEET 17UF 26 ATBCINC Fig 'ATBCBI/Q ATBCBO/Q ATBCR ST ATBCEQZ 1 o o 1 1 1 Q- LOCATORVALUEATIH 1 I 0 0 I 1 1 LOCATORVALUEATIHH THE ABOVE LOOK-AH EAD IS GOOD FOR CORRECTION IN v BITS I 5H, BIT O LOOK-AHEAD MUST BE OBTAINED DURING READ-FILLING AT SC538 0 III! Q EIBHEEH CWG AT READ FILLING S6538 C =I 0 O I I I 0 O I I LOCATOR VALUE AT SHIFT COUNT F/g. 3Q

PATENIEDAPR3 1975 ,725, 59

SHEET 180E 2s ATBLLCO/ ATBLCINC- ATBLCDEC- ATTBLCO ATBLC1/ INC Q ATBL 0 0/ Q 'ATT BL c1 A'rBLco/Q- TBLCO/Q BLCI/Q ATBLC2/ DEC ATTBLCZ ATBLCO/Q- vcc INC ATBLC3/ BLCO/Q Q DE C ATT BL C3 ATBLCO/Q- AT BLCE NA AT BL CR ST 

1. A data communication system comprising: a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, and means responsive to said indicating means indicating a burst error and said record means recoding only one burst error for correcting the burst error in said data segment at the address indicated in said burst error address register with the parity word generated by said parity word generator.
 2. The data communication system claimed in claim 1 having means to determine the number of bits in a burst error to be corrected.
 3. A data communication system comprising: a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said recording means recoding only one burst error for shifting said data segment out of said shift register one bit at a time, said shift counter responsive to shift of data bits out of said shift register for counting said bits of data, means for comparing the count of bits shifted out of said shift counter with the contents of said burst error address register and indicating a match between them, and means responsive to the indication of a match by said comparison means for exclusive oring said data bits and saId corresponding parity word to complement said burst errors.
 4. The data communication system claimed in claim 3 including a burst length counter set to a predetermined count by the indication of a burst error, means responsive to the shift of bits out of said shift register after the indication of a burst error for decrementing said burst length counter, and means responsive to said burst length counter when it has been decremented to zero for inhibiting the exclusive oring of said data bits and said corresponding parity word. 